In the sector of integrated circuits, techniques associated with utilization of resistance elements in such circuits become more and more important as the integration thereof is improved.
A resistance element structure of a prior art semiconductor device is that, as illustrated in FIG. 2, a low resistance region 108, serving as a wiring, into which impurities such as phosphorus and boron are implanted and a high resistance region 109 containing no or a slight amount of impurities are formed together with an element (e.g., a wiring) 104 thereunder, with only an insulating film being sandwiched therebetween.
A dominant memory cell of a conventional static RAM may be a high resistance polycrystalline silicon load type memory cell (e.g., Japanese Patent Laid-Open Publication No. 57-130461). As depicted in FIG. 7, the high resistance polycrystalline silicon load type memory cell incorporates a flip-flop for storing information, the arrangement being such that one inverter is composed of a MOSFET Q.sub.1 and a high resistance polycrystalline silicon resistance (high resistance region) R.sub.1, the other inverter is composed of a MOSFET Q.sub.2 and a high resistance polycrystalline silicon resistance (high resistance region) R.sub.2, and an output of one inverter is connected to an input of the other inverter. The flip-flop is combined with switching MOSFETs Q3 and Q4 for transferring or receiving pieces information to or from a unit outside the cell. A power supply V.sub.DD is connected to one end of each of the high resistance polycrystalline silicon resistances R.sub.1 and R.sub.2, while sources of the MOSFETs Q.sub.1 and Q.sub.2 are respectively connected to ground. A word line WL is connected to gates of the switching MOSFETs Q.sub.3 and Q.sub.4, while data lines DL and DL are connected to the drains thereof.
The high resistance polycrystalline silicon resistances R.sub.1 and R.sub.2 are formed, for instance, in the following manner. Formed on a semiconductor substrate are the MOSFETs Q.sub.1 through Q.sub.4 in which a first layer, i.e., a polycide film serves as a gate. Subsequently, an inter-layer insulating film is formed, and thereafter a non-doped, viz., intrinsic polycrystalline silicon film is formed over a surface of this inter-layer insulating film. A surface of a region including a portion which will hereinafter become a high resistance polycrystalline silicon resistance (high resistance region) in the intrinsic polycrystalline silicon film is covered with a mask layer by which the phosphorous is diffused into the polycrystalline silicon film, or alternatively ion implantation is effected thereinto. The resistance is thus reduced in value. The next process is to eliminate the mask layer, and the polycrystalline silicon film undergoes patterning to assume a predetermined configuration, thereby forming a wiring consisting of an N.sup.+ type polycrystalline silicon film exhibiting a low resistivity due to the introduction of phosphorus and also high resistance polycrystalline silicon resistances R.sub.1 and R.sub.2 each consisting of an intrinsic polycrystalline silicon film.
However, the following problems inherent in the foregoing conventional techniques arise. There will now be made some examinations about an increase and a decrease in a consumption current I.sub.DDS (flowing from the power supply V.sub.DD to a ground conductor via R.sub.1 or R.sub.2 during a so-called standby period) during the standby period (standby current) in the static RAM including the above-described high resistance polycrystalline silicon load type memory cell.
In the case of, e.g., a 256KSRAM or a 1MSRAM, the consumption current I.sub.DDS is typically some 1 .mu.A, and a potential difference between V.sub.DD and V.sub.SS is approximately 5 V.
Reducing the consumption current I.sub.DD may merely require a step of decreasing a film thickness of each of the high resistance polycrystalline silicon resistance R.sub.1 and R.sub.2. This implies that resistance values of the resistances R.sub.1 and R.sub.2 increase. The resistances, however, tend to receive an influence of an electric field of the element disposed thereunder as the film thickness is reduced. Thus, a so-called polycrystalline silicon thin film transistor structure is developed, wherein the wiring layer serves as source and drain regions, the high resistance polycrystalline silicon resistances R.sub.1 and R.sub.2 are conceived as substrates, and the element provided there beneath is a gate electrode. It therefore follows that the resistance values of the high resistance polycrystalline silicon resistances R.sub.1 and R.sub.2 vary (referred to as a TET effect) depending on a state of the electric field of the element thereunder. This approach is a technique disclosed in Jpn. J. Appl. Phys. 23 (1984) L819 and 24 (1985) L4345, written by Hayashi, Noguchi and Ohshima.
Hence, it is difficult to manufacture a thin film silicon resistance element having a high resistance value with stability on the basis of the conventional techniques. This difficulty in turn causes such a problem that a high resistance polycrystalline silicon load type static RAM exhibiting characteristics of a low and stable consumption current I.sub.DDS is hard to be manufactured.
Accordingly, it is a primary object of the present invention, which is devised to obviate the foregoing problems, to provide a thin film silicon resistance element having a stable resistance value, and further a structure of a static RAM having a low and stable consumption current I.sub.DDS.